vdakaKód: Vybrať všetko
if b <= 7 then
if to_integer(to_unsigned(b, 16)sll 13) <= a then
r13 <= a - to_integer(to_unsigned(b, 16)sll 13);
else
r13 <= a;
end if;
else
r13 <= a;
end if;VHDL kod
VHDL kod
zdar, potrebujem vediet, co urobit tato cast kodu, priblizne viem co to je, len to potrebujem vediet naisto vdaka
vdaka
Re: VHDL kod
Asi nejako takto (prepis do C)
Kde to to_unsigned prevedie b do 16 bitového unsigned čísla.
Takže ak je b menšie alebo rovné 7 (tj max 3 bity), tak tie tri bity presuň na najvyššie bity (tj. posun o 13 doľava) a tak ďalej...
A nabudúce kód do tagu CODE, tak ako ja.
Kód: Vybrať všetko
if( b <= 7 )
{
if( ((unsigned)b << 13) <= a )
r13 = a - ((unsigned)b << 13);
else
r13 = a;
}
else
r13 = a;
Takže ak je b menšie alebo rovné 7 (tj max 3 bity), tak tie tri bity presuň na najvyššie bity (tj. posun o 13 doľava) a tak ďalej...
A nabudúce kód do tagu CODE, tak ako ja.
Re: VHDL kod
tak sa spytam este raz nieco niekto s trochou casu a znalostou vhdl, vedeli by ste mi vysvetlit, ako tento algoritmus funguje, ak by mal niekto zaujem mi pomoct, tak poprosim o vysvetlenie, napr mi pride a,b=5. dakujem oh, zabudol som vlozit kod xD
niekto s trochou casu a znalostou vhdl, vedeli by ste mi vysvetlit, ako tento algoritmus funguje, ak by mal niekto zaujem mi pomoct, tak poprosim o vysvetlenie, napr mi pride a,b=5. dakujem oh, zabudol som vlozit kod xDKód: Vybrať všetko
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Modulo is
Port ( a : in integer range 0 to 65535;
b : in integer range 0 to 65535;
y : out integer range 0 to 65535);
end Modulo;
architecture Behavioral of Modulo is
signal r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1 : integer range 0 to 65535;
begin
process(a,b)
begin
if b <= 7 then
if to_integer(to_unsigned(b, 16)sll 13) <= a then
r13 <= a - to_integer(to_unsigned(b, 16)sll 13);
else
r13 <= a;
end if;
else
r13 <= a;
end if;
if b <= 15 then
if to_integer(to_unsigned(b, 16)sll 12) <= r13 then
r12 <= r13 - to_integer(to_unsigned(b, 16)sll 12);
else
r12 <= r13;
end if;
else
r12 <= r13;
end if;
if b <= 31 then
if to_integer(to_unsigned(b, 16)sll 11) <= r12 then
r11 <= r12 - to_integer(to_unsigned(b, 16)sll 11);
else
r11 <= r12;
end if;
else
r11 <= r12;
end if;
if b <= 63 then
if to_integer(to_unsigned(b, 16)sll 10) <= r11 then
r10 <= r11 - to_integer(to_unsigned(b, 16)sll 10);
else
r10 <= r11;
end if;
else
r10 <= r11;
end if;
if b <= 127 then
if to_integer(to_unsigned(b, 16)sll 9) <= r10 then
r9 <= r10 - to_integer(to_unsigned(b, 16)sll 9);
else
r9 <= r10;
end if;
else
r9 <= r10;
end if;
if b <= 255 then
if to_integer(to_unsigned(b, 16)sll 8) <= r9 then
r8 <= r9 - to_integer(to_unsigned(b, 16)sll 8);
else
r8 <= r9;
end if;
else
r8 <= r9;
end if;
if b <= 511 then
if to_integer(to_unsigned(b, 16)sll 7) <= r8 then
r7 <= r8 - to_integer(to_unsigned(b, 16)sll 7);
else
r7 <= r8;
end if;
else
r7 <= r8;
end if;
if b <= 1023 then
if to_integer(to_unsigned(b, 16)sll 6) <= r7 then
r6 <= r7 - to_integer(to_unsigned(b, 16)sll 6);
else
r6 <= r7;
end if;
else
r6 <= r7;
end if;
if b <= 2047 then
if to_integer(to_unsigned(b, 16)sll 5) <= r6 then
r5 <= r6 - to_integer(to_unsigned(b, 16)sll 5);
else
r5 <= r6;
end if;
else
r5 <= r6;
end if;
if b <= 4095 then
if to_integer(to_unsigned(b, 16)sll 4) <= r5 then
r4 <= r5 - to_integer(to_unsigned(b, 16)sll 4);
else
r4 <= r5;
end if;
else
r4 <= r5;
end if;
if b <= 8191 then
if to_integer(to_unsigned(b, 16)sll 3) <= r4 then
r3 <= r4 - to_integer(to_unsigned(b, 16)sll 3);
else
r3 <= r4;
end if;
else
r3 <= r4;
end if;
if b <= 16383 then
if to_integer(to_unsigned(b, 16)sll 2) <= r3 then
r2 <= r3 - to_integer(to_unsigned(b, 16)sll 2);
else
r2 <= r3;
end if;
else
r2 <= r3;
end if;
if b <= 32767 then
if to_integer(to_unsigned(b, 16)sll 1) <= r2 then
r1 <= r2 - to_integer(to_unsigned(b, 16)sll 1);
else
r1 <= r2;
end if;
else
r1 <= r2;
end if;
if b <= r1 then
y <= r1 - b;
else
y <= r1;
end if;
end process;
end Behavioral;
Re: VHDL kod
čo sa v tom kóde snažíš dosiahnuť?